god i just wanna be a better person so god help me

kadang gwe cape ama idup gwe tekanan kada ada di muka gwe kadang gwe pengen jerit sekenceng2nya buat ngilsngi stress gwe ntah apa


arghhhhhhhhhh gwe pengen semua hal2 yang gak penting di idup gwe itu pegi gitu aja karna gwe pengen idup gwe jadi ber makna gwe bosen idup kaya gin gwe pengen jadi sesuatu
tapi susah susah banget haha
sebenrnya di hati kecil gwe gwe pengen bikin mereka bangga dengan keberadaan gwe gwe pengen nyokap gwe senyum klo inget gwe gwe penggen adek gwe bangga klo nyeritaim gwe ama temn2 nya gwe pengen kk gwe mbk gwe juga bangga ama gwe






tapi entah lah munkin karna gwe yang terlalu bodoh jadi gwe susah buat bikin mereka bahagia karna gwe


ya allah tolong bantu gwe
gwe penggen bangt jadi orang baik
jadi sesuatu
plise god

kangen

kangen bgt ama bokap dah bebulan2 g ketemu ....
pgen rasanya gwe ktmu dia tapi gwe g tw dia dmn

hah.... kadang gwe berfikir untuk melupalan dia karna kesalahan nya tapi jujur gwe g bisa ...
jauh di hati gwe , gwe sanyang bgt ama bokap gwe...
g ada nama mantan bokap ...
ya mungkin gwe g bakal ketemu dia tapi doa gwe tetep ada buat dia...

jogja part2

lagi???1!!!!!!
oh god
sebenernya masih kebayang gimana g enaknya naek mobil 24 jam nonstop
tapi g papa lah ya
jogja aldo will be back

jogja im here

seneg baget sekarang age di jogja
and this is my firs time for me nulis blog di warnet yang ada di jogja
sebenernya gak ada yang beda dari warnet di lampung tapi keren aja
tunggu ya jogja gwe bakalan muterin lo ampe puas
and temen2 gwe tunggu kedatangan ku ya
hahahhahahhahha

uas coming soon

bentar lagi senen ugh,,, mou uas,
kalo hari pertama nya yakin bakalan lancar hahaha......
tapi dong,,,
pemrograman delpi,statistik,ama pbd,nilainyabelom aman jadi harus kerja keras,,,,,,,
god help me,,,,,,,,,,,,

pipelining

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Basic five-stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). The vertical axis is successive instructions, the horizontal axis is time. So in the green column, the earliest instruction is in WB stage, and the latest instruction is undergoing instruction fetch.

An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput (the number of instructions that can be executed in a unit of time).

The fundamental idea is to split the processing of a computer instruction into a series of independent steps, with storage at the end of each step. This allows the computer's control circuitry to issue instructions at the processing rate of the slowest step, which is much faster than the time needed to perform all steps at once. The term pipeline refers to the fact that each step is carrying data at once (like water), and each step is connected to the next (like the links of a pipe.)

The origin of pipelining is thought to be either the ILLIAC II project or the IBM Stretch project. The IBM Stretch Project proposed the terms, "Fetch, Decode, and Execute" that became common usage.

Most modern CPUs are driven by a clock. The CPU consists internally of logic and memory (flip flops). When the clock signal arrives, the flip flops take their new value and the logic then requires a period of time to decode the new values. Then the next clock pulse arrives and the flip flops again take their new values, and so on. By breaking the logic into smaller pieces and inserting flip flops between the pieces of logic, the delay before the logic gives valid outputs is reduced. In this way the clock period can be reduced. For example, the RISC pipeline is broken into five stages with a set of flip flops between each stage.

1. Instruction fetch
2. Instruction decode and register fetch
3. Execute
4. Memory access
5. Register write back

Hazards: When a programmer (or compiler) writes assembly code, they make the assumption that each instruction is executed before execution of the subsequent instruction is begun. This assumption is invalidated by pipelining. When this causes a program to behave incorrectly, the situation is known as a hazard. Various techniques for resolving hazards such as forwarding and stalling exist.

A non-pipeline architecture is inefficient because some CPU components (modules) are idle while another module is active during the instruction cycle. Pipelining does not completely cancel out idle time in a CPU but making those modules work in parallel improves program execution significantly.

Processors with pipelining are organized inside into stages which can semi-independently work on separate jobs. Each stage is organized and linked into a 'chain' so each stage's output is fed to another stage until the job is done. This organization of the processor allows overall processing time to be significantly reduced.

Unfortunately, not all instructions are independent. In a simple pipeline, completing an instruction may require 5 stages. To operate at full performance, this pipeline will need to run 4 subsequent independent instructions while the first is completing. If 4 instructions that do not depend on the output of the first instruction are not available, the pipeline control logic must insert a stall or wasted clock cycle into the pipeline until the dependency is resolved. Fortunately, techniques such as forwarding can significantly reduce the cases where stalling is required. While pipelining can in theory increase performance over an unpipelined core by a factor of the number of stages (assuming the clock frequency also scales with the number of stages), in reality, most code does not allow for ideal execution.

19 resolusi di 2009

1.gwe pengen ip gwe di atas 3.6
2.gwe pengen jadi penyiar radio
3.gwe pengen ngebemukin badan
4.gwe pengen solat gwe nggak penah ketinggalan
5.gwe pengen ngebeliin nyokap cincin
6.gwe pengen ganti komputer or beli laptop pake duit sendiri
7.gwe pengen liburan bareng ama sahabat2 gwe
8.......
di piirin lagi ya
19.